1. Field of the Invention
The present invention generally relates to a method for filling a metal in a narrow recess. In particular, the present invention is directed to a method for filling a metal in a narrow recess through a cleaning step to simultaneously remove residues in the recess and to substantially enlarge the opening of the recess at the same time.
2. Description of the Prior Art
In the standard semiconductor process, a material such as W or Cu is frequently used to fill up a hole to form a bridge for electrical connection, such as elements called conductive plugs or via plugs. This standard semiconductor process is getting more and more difficult as the critical dimension of the semiconductor elements is shrinking.
For example, in a substrate with a metal material layer and a dielectric layer covering the metal material layer a conductive medium is needed to be formed to penetrate the dielectric layer so that the metal material layer which is beneath the dielectric layer may form an upward electrical connection, or a via plug for use in a damascene structure may be formed. FIGS. 1-4 illustrate a conventional method to form a via. First, as shown in FIG. 1, a substrate 101 is provided. There is a metal material layer 110 in the substrate and a dielectric layer 120 covers the substrate 101. The dielectric layer 120 entirely covers the underlying metal material layer 110. Second, as shown in FIG. 2, a patterned photoresist layer 130 is formed on the dielectric layer 120 in advance. Next, as shown in FIG. 3, the patterned photoresist layer 130 formed in advance is used in an etching step to etch the dielectric layer 120. The resultant via 121 must expose the underlying metal material layer 110 which is deeply buried in the dielectric layer 120. Later, as shown in FIG. 4, a conductive material 122, such as Cu fills the resultant via 121 to form the needed conductive medium by methods such as deposition, sputtering or electroplating . . . etc.
The above-mentioned procedures are not too difficult when the critical dimension of the semiconductor elements has not been decreased too much, so the yield is stable and acceptable. However, it is getting more and more difficult to fill the via with the conductive material 122 and the yield drops quickly since the critical dimension of the semiconductor elements is decreasing too much. In particular, it is found that there are often voids 123 which seriously jeopardize the conductivity of the via 121 in the via 121 filled with the conductive material 122, as shown in FIG. 4. Accordingly, the conductive material 122 cannot serve as a proper conductive medium as expected.
On the other hand, the afore-mentioned etching step also leaves some problematic residues 124 in the via 121, as shown in FIG. 3. As the critical dimension of the semiconductor elements is downscaling, it is getting harder and harder to completely get rid of the residues 124. The residues 124 which block the via 121 not only adversely affect the performance of the conductive material 122 in the via 121, but also block the bottom of the via 121 so that a good electrical connection between the conductive material 122 and the underlying metal material layer 110 cannot be properly formed, and further, the device as a result fails. These problems still need to be resolved.